The present invention relates generally to defect detection in semiconductor device manufacturing, and, more particularly, to a test structure for determining open and short circuits in semiconductor devices.
For advanced integrated circuit process, the wiring line width can be tens of nanometers. As a result one issue during production is electrical opens in the wiring lines. Electrical opens occur due to defects such as hollow metal, stress voiding, missing patterns and other process errors. Additionally, electrical shorts occur due to defects such as metal debris or out-diffusion between wiring lines. It is critical to have methods and test structures on the wafer to test for these errors in the production process which allows the production team to detect when an error occurs prior to completing the manufacture of the entire wafer.
As part of the process monitoring and inline test for product chips, specially designed structures are often placed in Kerf areas, which are between functional dies and will be cut out during the dicing process. Such test structures should facilitate maximizing the efficiency of detection for shorts and opens by allowing for as many tests as necessary, using a minimal amount of area, while still detecting all defects of concern with minimal “escapes” (i.e. missed defects).
Certain test structures for wiring line in existence, such as comb structures for example, are configured to detect short circuits. Other test structures may be a serpentine structure, hybrid serpentine structures made up of serpentine structures and comb structures to detect both short and open circuits, and finally spiral structures such as that found in U.S. Pat. No. 7,187,179, entitled, “Wiring Test Structure for Determining Open and Short Circuits in Semiconductor Devices”.
The current structures for open and short defect monitoring are designed for contact DC probing, where metal probes are brought in electrical contact with probe pads in order to detect open and short circuits. DC probing may subject the wafer to mechanical damage in low-k dielectrics and metal layer causing yield and reliability issues in advanced technologies. In addition metal probe pads (typically 60 um×80 um each) take significant space in the kerf area.